High voltage 4H-silicon carbide ACCUFETs

Silicon carbide (SiC) is a promising material for high voltage, high frequency and high temperature semiconductor devices. The commercial availability of 6H- and 4H-SiC substrates, and the development of process technology for SiC, has led to demonstrations of a variety of SiC devices and circuits. In this research, a novel planar vertical MOSFET structure called the Accumulation Channel Field Effect Transistor (ACCUFET), which eliminates both the problems of premature oxide breakdown and low inversion layer mobility commonly found in SiC trench MOSFETs, is studied on 4H-SiC.; An investigation of the poor performance of previously fabricated 4H-SiC ACCUFETs provided insights for changes in device design and process flow for improving the device performance. This insight was used for designing a new process run for the fabrication of improved high voltage 4H-SiC ACCUFETs. These new designs of ACCUFETs were successfully fabricated on starting material with different epilayer thickness and doping values, corresponding to breakdown voltages ranging from 2000 V to 7500 V. The forward conduction characteristics of different ACCUFET designs were studied. The device physics and the operation of the planar ACCUFET are discussed in detail, and the effects of key device design parameters on device characteristics are described with the aid of two-dimensional simulations.; The contributions of the parasitic JFET regions (a surface JFET and a buried JFET) in the ACCUFET to its forward conduction and forward blocking characteristics are discussed in depth for the first time. ACCUFET structures designed for studying and for eliminating the problems due to the parasitic JFET regions are explained. It is demonstrated that in the high voltage ACCUFETs in which the epilayer doping is low, the buried JFET can be completely pinched off, resulting in a drain offset voltage in the current-voltage characteristics, which can be explained by the triodelike behavior of the buried JFET. The buried JFET regions of high voltage ACCUFETs are recommended to be wide and have a high doping density.; Further, an analytical model for evaluating the different components of the on-resistance of the planar ACCUFET is presented. This model is used to estimate the contribution of the individual components of the device on-resistance, and to make recommendations for proper engineering of the ACCUFET to meet its application requirements. In the fabricated 4H-SiC ACCUFETs, the channel resistance was found to be the most dominant among the on-resistance components, and is typically at least an order of magnitude higher than the remaining components. The huge channel resistance is attributed to a small effective channel mobility and a large threshold voltage, caused by a high density of traps at the SiO₂/SiC interface.; The analysis of the device on-resistance has demonstrated the need for sub-micron design rules for fabrication of high voltage 4H-SiC ACCUFETs with low specific on-resistance. The tighter design rules are shown to result in smaller channel lengths, cell widths, and source widths, all of which are desirable for obtaining low on-resistance.; The electrical properties of 4H-SiC ACCUFETs fabricated on different starting materials vary considerably, which are presented and discussed. The best measured room-temperature specific on-resistance of the 4H-SiC ACCUFET is about 25× lower than the existing real Si devices with the same voltage rating. At 200°C, the on-resistance of this device is approximately 250× lower than the real Si devices of the same voltage rating.