| Continuous scaling of very large scale integrated (VLSI) circuits poses severe thermal problems, which have major implications for performance and reliability in high-performance planar (2-D) integrated circuits (ICs) and emerging circuit architectures, such as vertically integrated (3-D) ICs. This dissertation aims to understand the thermal conduction phenomena from the fundamental material level to the system level and provides guidelines to the robust thermal design of VLSI circuits and systems. Accurate analytical thermal models for estimating the spatial temperature distributions along interconnects and vias have been presented, and verified by three-dimensional electrothermal simulations based on finite-element methods (FEM). This model, incorporating both interconnect and via self-heating effects, showed that localized hot spots and spatial temperature distributions in the interconnect structures are strongly affected by various geometric and material parameters. In addition, a rigorous scaling analysis of multilevel interconnect temperatures has been performed using 3-D electrothermal FEM simulations, combined with accurate calculations of resistivity of copper, thermal conductivity of low-k interlayer dielectrics (ILD), and various scaling factors. Comprehensive scaling analysis has showed that the interconnect temperature rise is expected to increase significantly in sub-50 nm technologies. As a potential cooling solution, conduction cooling offered by novel multilayered substrates has been investigated by measuring the thermal conductivity of a novel multilayer substrate using a harmonic Joule heating technique. Finally, the thermal analysis of both 2-D and 3-D ICs has been presented, providing chip-level thermal management strategies in high-performance VLSI circuits and systems. |
