| The execution performance of Java has been one of the most important issues since it was introduced worldwide. In order to achieve the Java speed-up, this research first demonstrates how to design a Java microprocessor in silicon to perform direct execution of Java bytecode instructions in hardware. By applying a top-down hardware design methodology to the FPGA design process, it becomes easier and more flexible to implement Java in a FPGA device. Next, an architectural view of a memory structure for embedded Java systems is presented by introducing a new, static Java class loader, i.e. Smart Loader. Smart Loader creates a new way of optimizing bytecode and memory structures. The experimental results show that Smart Loader, with an advanced memory architecture, can achieve instruction savings up to more than 20% and reduce the memory accesses. For the next approach, an advanced, dynamic bytecode instruction-folding process for Java processors has been developed. SPEC JMV98 benchmark results show that the proposed POC (Producer, Operator, Consumer) model-based folder can save more than 90% of the folding operations. Finally, this research attempts to solve the performance problem by improving Instruction Level Parallelism (ILP) combined with the newly developed instruction folding technique. An experiment using SPECJVM98 benchmarks reveals that as many as 7.8 bytecode instructions can be executed concurrently. Ultimately, the proposed optimization techniques in this research can eliminate most of the time-consuming Java operations and redundancies, and can thereby achieve the performance of high-end RISC processors. |
