Mechanical and electromechanical studies toward the assembly of carbon nanotube-based nonvolatile random access memory

An approach toward the assembly of a fully integrated electromechanical random access memory (RAM), which uses carbon nanotubes and other 1D inorganic nanowires as memory elements and as their own I/O lines, has been developed. It is based on a suspended crossbar architecture of single-walled carbon nanotubes in which information is stored as the electrical junction resistances. The bit states can be changed reversibly by the electrostatic actuation of the upper suspended nanotube segments into and out of mechanical contact with the lower nanotubes or nanowires. Van der Waals adhesion forces stabilize the mechanically strained ON states so that information is stored in a nonvolatile way, i.e. the bit state is retained without power. In silicon-based DRAM (dynamic RAM) the stored information is lost if the bits are not recharged frequently.; It was found experimentally that only carbon nanotubes can elastically withstand the tensile strains necessary to operate our electromechanical RAM architecture. The validity of our approach toward an electromechanical nanotube based RAM was demonstrated both by quantitative calculations and by the assembly of proof-of-principle bits. Finally, various assembly strategies toward small arrays of electromechanical nanotube- or nanowire-based bits were pursued.; Our approach toward an integrated nanotube-based RAM architecture is unique since it provides a strategy to assemble molecular-sized bits and integrate them with I/O lines. These nanotube-based memories could be chemically self-assembled at a Tbit/cm2 integration density and operate at bandwidths exceeding 100 GHz. Thus, our architecture could overcome the limitations of silicon-based dynamic access memory (DRAM) in size, speed and cost. Furthermore, nanotube-based RAM is nonvolatile: it combines the permanent data storage capabilities of magnetic hard disks with an access speed superior to that of silicon-based DRAMs, thus making it an ideal memory.