| The use of high-speed arithmetic units is vital for processors designed to execute arithmetic-intensive applications, such as digital signal processors (DSPs) and multimedia processors (MMPs). As arithmetically-intense applications become mainstream, the area, delay, and power consumption requirements for such arithmetic processors become more stringent. Although several algorithms have been developed for designing efficient arithmetic units, new algorithms and hardware designs are needed to meet the requirements of emerging applications.; This dissertation investigates the design, implementation, and evaluation of arithmetic units for digital signal processing and multimedia. These arithmetic units include reciprocal, reciprocal square root, square root, squaring, and multiply units. Novel algorithms and hardware designs for these arithmetic units are developed. A key feature of these algorithms is that they use detailed error and logic analysis to reduce the area, delay, and/or power consumption. To evaluate the efficiency of these algorithms with respect to conventional methods, hardware designs for IEEE single precision floating point arithmetic units are realized using Verilog and the Synopsys Module Compiler tool suite. The area, delay, and power consumption of these implementations are then compared to those of conventional arithmetic units. Each algorithm and hardware design provides a substantial reduction in area, delay, and/or power compared to conventional units with the same functionality, while maintaining comparable qualities of the attributes not being optimized. |
