| The design of high-end microprocessors is increasingly constrained by high levels of power consumption. In this dissertation, we propose several microarchitectural-level, technology-independent solutions for reducing the power requirements of a superscalar microprocessor without seriously impacting its performance. First, we introduce a mechanism to dynamically allocate processor's resources to adjust to the demands of executing applications. Our approach allocates "just the right amount of resources at the right time" by periodic sampling of resource occupancies and deactivating the underutilized resource partitions. Additional mechanism is used for performing resource allocations when the application requirements increase. Our technique results in 36% of dynamic energy savings within the issue queue, 73% of energy savings within the reorder buffer and 20% reduction in energy within the load-store queue. This is achieved with only moderate increase in the layout area and the performance degradation of as low as 2% on the average across SPEC 2000 benchmarks.; Second, we describe a technique for reducing the datapath power requirements in processors that use a separate (architectural) register file (ARF) for holding committed values. The proposed mechanism exploits the notion of short-lived operands---values that target architectural registers that are renamed by the time the instruction producing the value reaches the writeback stage. The idea is to avoid unnecessary writebacks into the result repository (a slot within the reorder buffer or a physical register) as well as writes into the ARF from unnecessary commitments by only caching (and isolating) short-lived operands within a very small dedicated register file. Dynamic energy reduction of 21% within the reorder buffer and the ARF can be achieved with the use of a 32-entry register file for holding short-lived operands.; Third, we propose a mechanism for reducing the power dissipation within the on-chip storage components by exploiting the lack of the data stream entropy. Specifically, we avoid the activation of byte slices containing all zeroes, particularly in the higher-order bytes of operand values that are read out from physical registers, issued to functional units, forwarded from function units or moved into the reorder buffer or the issue queue. (Abstract shortened by UMI.)... |
