Advanced SoC design methodology for wire-speed packet forwarding in Internet switches

Key network and system architecture issues for the deployment of converged Internet Protocol networks require Wire-Speed packet processing at optical rates to enable emerging real time services such as packet voice. Heterogeneous systems on chip are key to delivering the required packet processing and forwarding performance. This work articulates an algorithm for the design and implementation of such systems-on-chip. Qualitative and Quantitative models for the forwarding data-path are developed and explored in detail. Both, Software micro-code based implementations and hardware based state machine implementations have been analyzed, and their respective tradeoffs have been identified. A 2.5 Gbps integrated scalable SoC targeted at a large packet voice gateway is used as a vehicle to validate the methodology. Measured results are presented and confirm the design methodology.