Physically-aware N-detect test

The main goal of manufacturing test is to separate functioning ICs from defective ones. A good testing process is the key to identify quality ICs to be shipped to downstream customers. As manufacturing technology advances, minimal feature size decreases and design complexity increases. Behaviors of defects encountered in the manufacturing process however are also becoming more complicated and harder to characterize. To cope with the ever-changing failure mechanisms exhibited by the scaling manufacturing processes, test methods have been evolving: simple test methods, which often require less cost, are no longer sufficient to maintain the desired quality level; complex test methods targeting specific failure behaviors may lead to better defect coverage at the expense of higher cost. Maintaining quality levels under acceptable test cost is thus more challenging. This necessitates new test approaches that can deliver high-quality tests capable of capturing emerging failure mechanisms in a cost-effective manner.;The PAN-detect test methodology is cost-effective for the following reasons. First, the underlying PAN-detect metric subsumes other static test methods, which reduces the cost from separately applying various test methods that each targets a different defect behavior. Second, test cost is considered by employing test selection with a test-set size constraint. Test selection is applicable to large designs and is therefore adopted to efficiently generate compact test sets. Utilization of existing tools also reduces test development time and cost. The generated, compact test sets can be further compressed to reduce test data volume (while maintaining the desired quality level), which alleviates the need for large tester memory and saves test time. Quality of the generated test sets can also be further enhanced without increasing test pattern count.;We also develop a general and efficient test-metric evaluation methodology for evaluating the effectiveness of a variety of test methods. The methodology enables rapid test evaluation by exploiting the readily-available test-measurement data in chip-failure log files resulting from the application of any set of test patterns. In other words, extra test development and application for the evaluated test methods are eliminated. Measures of test effectiveness and insufficiencies learned from test-measurement data provide guidelines for selecting a best mix of test methods to be applied and for developing new test methods. The test-metric evaluation methodology therefore facilitates test-method development by efficiently closing the test-evaluation development loop, which used to be costly and time consuming.;The effectiveness and applicability of PAN-detect and the test-metric evaluation methodology are demonstrated through a series of experiments using both simulation and tester responses from real ICs. The PAN-detect test methodology is used to generate a test set that is included in the production test of an IBM ASIC. Experiment results demonstrate the effectiveness of PAN-detect test in detecting defects encountered in modern manufacturing processes. The test-metric evaluation methodology is further used to compare PAN-detect with other test methods using failure logs from an LSI test chip, an IBM ASIC, and an NVIDIA GPU. Results reveal that PAN-detect test outperforms other test methods in capturing chip failures.;In this dissertation, we develop a general, physically-aware N-detect (PAN-detect) test methodology that generates compact, high-quality test sets. The test methodology enhances test quality by utilizing a PAN-detect metric that exploits defect locality. In PAN-detect, signal lines that are most likely to influence a targeted line involved in a defect are considered, and various defect activation and propagation conditions are explored. The likelihood of detecting unmodeled defects is therefore increased.