Post route clock tree analysis at multi-GHz with inductance effect

As CMOS technology advances into Deep Sub-Micron (DSM) design and as the operating clock frequencies of DSM chips goes beyond 109 Hz, the delay associated with interconnects has an increasingly dominant impact on the overall propagation delay of the clock distribution network [1]. The clock signal is one of the most important signals in a digital synchronous system. A clock signal is typically loaded with the greatest fan-out, travels over the longest distances, and operates at the highest speed within the entire system [1]. Therefore, in order to design clock distribution networks properly, more accurate interconnect models are required [2].; Currently, all the available EDA tools model the interconnect effect as either capacitive (C) or resistive/capacitive (RC) effect. However, as the systems begin to operate at higher frequencies, the inductance (L) effect can no longer be ignored [1]. In CMOS DSM VLSI circuits, interconnect delay for clock trees can be more accurately modeled by RLC trees [3]. In this dissertation, we present a methodology for extracting the inductance value of the interconnect segments for clock networks. A new on-chip interconnect extraction approach is proposed to calculate accurate and efficient parasitic inductance values. This extraction methodology considers the skin effect on the interconnect resistance and inductance.; Analysis for various clock distribution methodologies and their effect on the on-chip inductance and crosstalk is presented in this dissertation. This analysis demonstrates a novel impedance based approach which approximates L-type RLC circuit equivalent values for both parallel and in-series RLC circuits.; Extracted inductance values obtained from our method are validated against values obtained from a field solver software for a large set of test cases. A comparison of run times between our method and the field solver reveals that our method is much faster and suitable to be utilized for Application Specific Integrated Circuits (ASIC) analysis. The accuracy of extracted values can be further improved by utilizing a fab provided S-parameter set to generate a process specific inductance formula.