Vertical surrounding-gate MOSFETs incorporating silicon germanium heterojunctions

As transistor scaling enters the sub-0.1μm regime, lithographic issues and poor short channel characteristics forecast limits to continued scaling. Transistor design for tomorrow's applications is turning to novel devices and nonstandard material investigation, including exploration of the vertical dimension, source/drain engineering, and heterostructure incorporation.; This work uses silicon germanium (SiGe) heterostructures in vertical surrounding-gate MOSFETs to tailor current-voltage characteristics by controlling physical effects in the device. The gate completely surrounds the channel yielding almost ideal subthreshold slopes and excellent short channel characteristics. The vertical channel facilitates direct channel profile engineering via epitaxial growth of SiGe heterostructures before pillar etch, giving designers an additional degree of freedom. Theoretically, SiGe incorporation in the source could delay the floating body effect (FBE) by reducing the parasitic bipolar junction transistor back injection efficiency and current gain. SiGe incorporation in the drain could modify hot carrier characteristics via material dependent impact ionization coefficients.; Vertical MOSFETs incorporating SiGe were initially explored by simulation. Varying SiGe layer thicknesses, locations, and germanium fractions were analyzed. Simulation predicted FBE suppression by the SiGe source layer, leading to increased transistor breakdown voltage. The effect is largest at low gate voltages where lateral electric fields dominate and breakdown is governed by current levels, which the SiGe affects directly. Simulation predicted increased impact ionization in SiGe drain layers, decreasing transistor breakdown voltage, which could find application in low voltage memory operation.; Fabrication of vertical MOSFETs proved the power of simulation tools for studying advanced devices. Characterization of doped SiGe epitaxy, oxidation, and dopant activation was performed to prevent SiGe strain relaxation. Devices with abrupt and ramped SiGe source layers showed 3V and 6V higher breakdown voltages at low gate voltages, respectively. SiGeC layers showed FBE kink delay. Devices with ramped SiGe drain layers showed increased drain current in soft breakdown, from increased impact ionization verified by substrate current measurement, with 1.5V lower breakdown voltages. Comparison of simulation to experiment displayed the difficulties of accurately predicting device parameters, but demonstrated the usefulness of simulation to qualitatively predict device behavior without costly expenditures of time, material, and equipment.