Superiority And Reliability Of MOSFETs With High Mobility Channel

With the continuous device scaling down as predicted and required by Moore’s law, the silicon complementary metal-oxide-semiconductor (CMOS) technology has been pushed down to 14 nm, approaching its physical limitations. Ever since the 90 nm technology node, purely scaling the channel length cannot ensure the performance enhancement of metal-oxide-semiconductor field effect transistor (MOSFET). The study of new technologies, including the strained silicon, high-k/metal gate technology, high mobility channel material, multi-gate structure, etc., have become more and more important. All these new technologies have been widely discussed and investigated. This thesis focuses on the study of reliability issue in strained Si devices and ultra-scaled SOI (Si-on-insulator) MOSFETs, carrier transport property of devices with high mobility channel as well as the Ge MOSFET with novel device structure.This thesis firstly studies the reliability issue in strained Si devices. It is found that the uniaxial tensile strain will alter the electrical property of front biased p-n junction. The current in the large-forward-bias region will increase a lot, while the current in the diffusion-current-dominant region will increase a little. The applied strain will decrease the ideality factor in both regions. The strain induced gate tunneling current (Ig) change is studied as well. The uniaxial and biaxial strain will decrease the Ig in inverted and accumulated nMOSFET while increase the Ig of pMOSFET. Then it is firstly proved in this thesis that the negative-bias-temperature-instability (NBTI) of pMOSFET will be intensified by uniaxial and biaxial tensile strain and alleviated by uniaxial and biaxial compressive strain. For the BTI of highly scaled SOI MOSFET, the experiment and simulation has proved that the MOSFETs with shorter channel will have a better BTI performance.This thesis also studies the carrier transport property in the Ge nMOSFET and SiGe pMOSFET. It is demonstrated, for the first time, that in Ge nMOSFETs, the dominant scattering mechanism in the high-normal-field region is not necessarily surface roughness scattering. In Ge(100) nMOSFETs, phonon scattering is dominant in the high-normal-field region. In contrast, the high-normal-field mobility in Ge(111) and Ge(110) nMOSFETs can be increased by Ge interface engineering because Ge(111) and Ge(110) are free of intervalley phonon scattering. Alloy scattering in sSi/Si0.5Ge0.5/sSOI QW p-MOSFETs is experimentally investigated by modulating the holes distribution through applying back-gate biases. It is found that the holes mobility is degraded in the low electrical field region by the intensified alloy scattering. In the high field region, alloy scattering has little effect on the mobility.For GeOI MOSFETs, it is shown that the accumulation mode (AM) nMOSFET and pMOSFET have higher drain current and carrier mobility. Electron mobility will increase under positive Vbg and decrease under negative Vbg. While hole mobility has the opposite dependence. The carrier mobility of AM MOSFETs will benefit more from Vbg. This thesis reports the first observation of RTN in Ge nano-wire (NW) nMOSFETs. The mobility fluctuation is confirmed to be the source of low frequency noise in ultra-scaled Ge NW nMOSFETs other than the carrier number fluctuation. Because of the long mean free path of electrons in Ge, the low frequency noise is suppressed at shorter channel due to the near-ballistic transport at sub-100 nra region. Therefore, ultra-scaled Ge NW MOSFETs with low channel doping, small EOT and high HNw are promising in the performance enhancement as well as the suppression of low frequency noise.