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Abstraction techniques for verification of digital designs

Posted on:2002-02-13Degree:Ph.DType:Dissertation
University:The University of Texas at AustinCandidate:Bhadra, JayantaFull Text:PDF
GTID:1468390011496949Subject:Engineering
Abstract/Summary:
Industrial designs are becoming more complicated as technology advances and demand for higher performance increases. The growing complexity poses an increasingly serious challenge towards avoiding design errors. Consequently, design verification forms an important task in the product development cycle. It is desirable to attain an acceptable level of confidence in a design as early in the development cycle as possible. This makes automatic verification methods quite popular as they are effective in discovering bugs with relatively low turn around time. However, as the design size grows, most techniques are adversely affected by the design state explosion problem. The main contribution of this dissertation is the development of automated problem. The fundamental idea is to formulate the behavior of a system in by analyzing the model.; for state explosion. We then present a technique to generate witnesses that enable the original design to exercise interesting control behavior. The second technique presented in the dissertation deals with verification of custom using regular expressions and an automatic method for constructing state machines that are useful in verifying equivalence between a register transfer language level description of a custom memory and a switch level description of the The effectiveness of the techniques presented in the dissertation has been demonstrated on real life industrial designs.
Keywords/Search Tags:Techniques, Verification
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