Low-power oversampled signal processing for digital radio receivers

Three techniques for reducing power consumption in oversampled receivers are developed: a method for improving the SNR attainable in power-efficient double-sampled {dollar}DeltaSigma{dollar} modulators; a combination of polyphase and multistage techniques to minimize power in decimation filtering; and a method of re-timing decimation to avoid the need for a re-sampling filter in the timing recovery circuits that follow the oversampled ADC.; An analysis of mismatch effects in double-sampled SC {dollar}DeltaSigma{dollar} modulators shows that the feedback path from the quantizer to the first integrator is dominant, and we show how to use a bilinear integrator circuit to obtain first-order noise shaping of this error. While conventional double-sampled circuits are limited to 12-bit resolutions with typical components, the new circuit can go to 16-bit or better in the presence of the same mismatches.; Cascaded accumulators (typical bit-width of 16{dollar}sim{dollar}24 bits) in a CIC decimator often dominate power consumption and limit clock rates. Simply using multi-stage CIC decimators is not a solution. A combination of multi-stage CIC decimators with polyphase techniques mitigates these problems. We show how to design multi-stage polyphase CIC decimators by considering aliasing rejection for interference and quantization noise, and by budgeting the word-length in each stage. We provide a design scheme to simplify polyphase components again down to a handful of gates. An FPGA implementation of a 100-MHz digital downconverter using the new design shows a 5x power saving. The technique makes low-power and GHz-rate decimators practical by reducing the peak rate.; In an oversampled receiver, we show that moving timing recovery function into an existing decimator offers the fine resolution required at a much lower cost than interpolation method. This allows us to adjust timing by a typical 1/64 of a symbol period. Simply shifting this clock phase is not a solution, however, because it produces large "glitches" at the output. We show that the glitch settles out after N (typically 3 or 4) samples, so that it can be eliminated by using a dual-differentiator decimator. We analyze timing jitter and SNR bound due to interferer mixing with jitter and show a good fit with simulation. One experiment shows that the SNR bound result is within 1.5 dB of consistency with the estimate. We verify the stability and validity of the circuit by implementing an FPGA chip for BPSK.