| Residue Number System (RNS) offers a promising future for highly parallel computing hardware because its carry-free operations in addition, subtraction and multiplication. However, unless the problems with its complex sign detection, number comparison, and division are solved, general computing RNS will not be reality. This dissertation work offers a solution to that problem and presents a prototype of RNS arithmetic logic unit (ALU), which is also capable to perform general division.; With the new technique in selecting moduli set proposed in this work, one can find a moduli set with any number of modulus, which can simplify sign detection in RNS. This, in turn, can improve the performance of number comparison, and with this progress, division in RNS can be done easily and fast.; The prototype of the ALU was implemented in two ICs, namely AU1 and AU2, based on moduli set {lcub}31, 15, 2{rcub}. AU1 is capable of performing RNS addition, subtraction and number comparison. The inputs to this IC are two RNS numbers, a 2-bit opcode, and clock. The outputs are one RNS number, which shows the result of the addition/subtraction 2-bit output for comparison results, and 3 status flags for zero, negative and overflow. The second chip, AU2, can perform RNS multiplication and division. The inputs to this IC are two RNS numbers, a 1-bit opcode, and clock. The outputs are one RNS number, which shows the product of the multiplication or the quotient of the division, and a status flag indicating the validity of the result.; All of the designs in this work were carried out in VHDL (Very-High-Speed-IC Hardware Description Language). The simulation and physical layout of the ICs were done using EDA software from Mentor Graphics, which includes Modelsim, Leonardo Spectrum, Quickpath, Quicksim, and IC Station. |
