High-frequency mixed-signal silicon on insulator circuit designs for optical interconnections and communications | Posted on:2003-05-10 | Degree:Ph.D | Type:Dissertation | University:University of Southern California | Candidate:Zhang, Liping | Full Text:PDF | GTID:1468390011480803 | Subject:Engineering | Abstract/Summary: | | This research explores architectures and design principles for monolithic optoelectronic integrated circuits (OEICs) through the design and implementation of (a) a parallel-pipelined media networking and signal processing network; and (b) low-power radio-frequency mixed-signal complementary metal-oxide semiconductor (CMOS) silicon-on-insulator (SOI) circuit and chip designs for wireless and optical communications fabricated in Ultra-Thin Silicon-on-Sapphire (UTSi®-SOS) technology.; A signal processing and networking platform called reconfigurable translucent smart pixel array (R-TRANSPAR) has been implemented. The system uses Honeywell 2D interlaced arrays of vertical-cavity surface-emitting lasers (VCSELs) and metal-semiconductor-metal (MSM) detectors for optical interconnections. The detected optical current is converted into voltage and amplified for further single-instruction multiple data (SIMD) signal processing and networking. Both free-space and image-fiber chip-to-chip communications have been demonstrated based on this platform. A novel 3D optical parallel data packet (OPDP) switching multi-token-ring network has been designed, implemented and demonstrated. Time-division multiplexed network node addressing technique is used to enhance channel utilization and throughput.; The ultimate goal of this research is to integrate monolithically silicon CMOS with optical devices. High throughput interconnections demand high sensitivity, low noise, high gain-bandwidth product transceivers. We have identified that ultra-thin silicon-on-sapphire as the most promising CMOS SOI technology because of its optically transparent, electrically full-insulating sapphire substrate and matched thermal expansion coefficients of sapphire with GaAs semiconductor optical devices.; Four mixed-signal chips have been designed and fabricated in 0.5 micron CMOS SOS technology through MOSIS. Two 2000 CMOS SOS smart-pixel array chips were designed for wire bonding and two recent SOS chips are designed for flip-chip bonding with VCSELs and photodetectors arrays. Novel monolithic PIN optical detector arrays have been designed and fabricated in UTSi-SOS technology. Various low-power and high frequency techniques including dynamic threshold voltage have been explored. Radio frequency (RF) transceivers arrays with built-in self-test (BIST) circuits, full monolithic photoreceivers, monolithic multi-GHz π/4 quadrature-phase voltage-controlled oscillators (VCOs), differential VCOs, mixers, baluns, and phase-locked loop based clock data recovery circuits have been designed and fabricated in CMOS SOS technology for wireless, optical interconnections and communications. | Keywords/Search Tags: | Optical, CMOS SOS, Communications, Circuits, Designed, Technology, Mixed-signal, Monolithic | | Related items |
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