Computer-aided fault to defect mapping (CAFDM) for defect diagnosis

Defect diagnosis in random logic is currently done using the stuck-at fault model, while most defects seen in manufacturing result in bridging faults. In this research we use physical design and test failure information combined with bridging and stuck-at fault models to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). We build on top of the existing mature stuck-at diagnosis infrastructure. The performance of the CAFDM software was tested by experiments at Texas Instruments and Intel by diagnosing controlled and production chips. The correct defect location and layer was predicted in all 9 control samples for which scan-based diagnosis could be performed. The experiment was repeated on production samples that failed scan test, with promising results.