| Microprocessor power dissipation is a growing concern, so much so that it threatens to limit future performance improvements. A major consumer of microprocessor power is the issue queue. Some microprocessors, such as the Compaq Alpha 21264 and IBM Power4, use a compacting latch-based issue queue design which has the advantage of simplicity of design and verification. The disadvantage of this structure, however, is its high power dissipation.; In this dissertation, we explore different issue queue power optimization techniques that vary not only in their performance and power characteristics, but in how much they deviate from the baseline latch-based implementation. As part of this effort, we develop a number of techniques including a non-compacting queue with novel selection logic that results in far less power than the conventional compacting approach with small performance loss. We also compare and evaluate the power savings of CAM/RAM-based issue queue designs over their latch-based counterparts. We propose a novel banked CAM/RAM-based issue queue that trades off a small performance degradation for an even greater power savings. We then describe the microarchitecture and circuit design of an adaptive issue queue that dynamically resizes the queue for power savings. Two different dynamic adaptation algorithms, using issue queue utilization and parallelism metrics, are compared. Furthermore, we propose a novel, complementary combination of fetch gating and issue queue adaptation to further reduce issue queue power in conjunction with overall microprocessor power dissipation. We introduce an issue-centric fetch gating scheme based on issue queue utilization and application parallelism characteristics. We then couple this issue-driven fetch gating approach with an issue queue adaptation scheme based on queue utilization. |
