A New Method for the Removal of Parasitic Capacitances from sub-100nm MOSFETs Using Low-Noise Split Capacitance-Voltage Measurements

The physical shape of MOSFETs and the processing involved in their fabrication give rise to parasitic capacitances. These capacitances are typically small compared to the intrinsic channel capacitance of the device, but as MOSFETs scale into the sub-100nm gate length range, the parasitic capacitances become a significant percentage of the overall measured capacitance, resulting in a source of error in the analysis of these devices. The purpose of this work is to describe these parasitic capacitances and their origin in MOSFET structures and to propose a method for their removal for analysis. The experimental devices used for this work are high-k/metal gate pMOSFETs of varying physical gate length, fabricated at the College of Nanoscale Science and Engineering's 300mm Silicon processing facility. The fabrication of the experimental devices is discussed in detail. By using split capacitance-voltage measurements, the channel capacitance, combined with the parasitic capacitances, is measured. The parasitic terms do not depend on the gate length of the devices, and by calculating the slope of the measured capacitance with respect to the gate length of the devices, the parasitic terms are removed. This method is demonstrated with the experimental devices and the intrinsic channel capacitance is separated from the parasitic capacitances, allowing for more accurate calculation of the effective mobility. The finite element modeling tool Sentaurus Workbench is used to model pMOSFET devices. The parasitic capacitance removal method is demonstrated on the simulated devices and results are compared to the experimental devices. The viability of the parasitic capacitance removal method and the behavior of the parasitic capacitances with respect to the applied gate voltage are discussed. Finally, results are summarized and future directions are proposed.