A high-speed, high-resolution sigma-delta modulator analog-to-digital converter

Sigma-delta modulators provide the means for achieving high-resolution analog-to-digital conversion. The main limitation faced in high-resolution Sigma-Delta approach is the conversion speed. A multi-stage multi-bit sigma-delta modulator with interstage gain scaling is proposed in this study and it is designed and implemented in a 0.6 mum CMOS process. This topology employs a second-order single-bit modulator in the main stage followed by an 8-bit quantizer in pipeline structure. The second stage of the modulator consists of a first-order single-bit modulator followed by a 5-bit quantizer. A gain stage is inserted between the two stages to scale the signal level to within the reference level.; System and circuit level simulations have demonstrated that the proposed modulator is capable of achieving high speed and high resolution of analog-to-digital conversion. The detailed design considerations in circuit implementation of the proposed modulator are also analyzed and discussed. The prototype is fabricated in a 0.6 mum CMOS process with 3.3V power supply. The experiment measurement of the prototype is performed. Several factors and issues limiting the achievable high performance are also discussed.