| Warp processors dynamically and transparently optimize an executing software binary by moving software kernels to on-chip configurable logic, improving performance by 6.4X and reducing energy consumption. Extensive research has shown that hardware/software partitioning, the process of dividing an application between software executing on a microprocessor and hardware co-processors, can result in overall software speedups as well as reducing system energy. However, such partitioning typically requires special desktop-based computer-aided design (CAD) tools and designer expertise. Instead, by developing a custom routing-oriented field programmable gate array (FPGA) and lean on-chip decompilation, partitioning, and just-in-time (JIT) FPGA compilation tools, warp processors provide the performance and energy benefits of HW/SW partitioning without any designer effort or expertise. Using warp processors, a designer can use any programming language and compiler to create a truly portable application binary. A warp processor will determine how to best execute the portable binary either as software executing on a processor, entirely in hardware using configurable logic, or partitioning the application between software and hardware. |
