| In today's world of advanced technology, numerous applications are computational intensive. This led to the development of new System-on-Chip (SoC) design techniques to allow for integration and reuse of Intellectual Property, IP Cores, under time-to-market pressure. A wide range of these newly emerging design platforms is now drifting towards highly integrated SoC designs with many on-chip processing resources like processors, DSPs, and memory. Using this technique, designers can build SoC by integrating dozens of IP cores. As the number of IP cores increases, the on-chip communication and physical interconnections become a bottleneck.; Originally, SoC was built based on a Bus-Centered approach. The Bus-Centered approach is a shared-medium architecture in which all IP cores share the same transmission medium. The Bus architecture is widely used in current SoC implementation and will continue to be the right design platform for small designs that integrate a few IP cores. However, for designs targeting FPGA with a large number of IP cores, we will propose a Micronetwork based System-on-FPGA (SoFPGA) architecture.; The problems with a SoC bus-centered approach using FPGAs grow as the size of the FPGAs and the complexity of the associated IP grows. The bus does not scale with the system size as the bandwidth is shared by all the components attached to it. Furthermore, smaller technologies are more subject to random errors and hence verification of physical faults will become increasingly more difficult. Also, as the number of IP cores increases, the capacitive load increases and the electrical performance degrades. Moreover, Synchronizing SoC with a single clock source and eliminating clock skew becomes extremely difficult or even impossible.; In this work, we will present a router architecture to be used as the basic building block of low overhead cost SoFPGA. This router is implemented as a VHDL model. We will address the interconnecting issues in SoFPGA design methodology built in a single FPGA device. Mainly, we will consider the problem of achieving efficient NoFPGA (Network-on-FPGA) performance through investigating the best topology. The hardware overhead induced by the 2D Mesh NoFPGA will be compared to the hardware overhead of the 2D Torus. |
