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Three-dimensional impedance engineering for mixed-signal system-on-chip applications

Posted on:2006-10-23Degree:Ph.DType:Dissertation
University:University of California, Los AngelesCandidate:Chong, KyuchulFull Text:PDF
GTID:1458390008953193Subject:Engineering
Abstract/Summary:
A novel approach for three-dimensional substrate impedance engineering of p-/p+ epi substrate is proposed for mixed-signal integrated circuit applications. This technology requires minimum intrusion to conventional Si CMOS processing, but offers astounding improvements with regard to RF crosstalk via substrate and RF passive device performance. The engineered substrate consists of conducting as well as semi-insulating regions strategically placed three-dimensionally throughout the volume of the substrate. The p-/p+ epi substrate is used to prevent latch-up at tight design rules in high performance digital CMOS. Metal vias are fabricated from the front side using electroless plating method for Faraday cage isolation structure as well as "true ground" contacts. A self-limiting micro-PS formation process is employed to allow the insertion of semi-insulating regions from the backside of the wafer and RIE etch to remove p- layer is performed from the front side completely eliminating any parasitic pathways for crosstalk.; The crosstalk isolation methods in this study are based on the principle of RF noise shielding in addition to insulating. Both the suppression of crosstalk by the metal vias and micro-PS trench isolation are so significant that the crosstalk goes down to the noise floor of the conventional measurement instruments. The use of micro-PS layer effectively can reduce the parasitic substrate effect. These reductions result in higher Q and fr of inductors on micro-PS region. Inductors located on micro-PS are subjected to a much less stringent set of constraints than that on bulk Si substrates, allowing for much higher inductance without severe sacrifice in Q and fr, and much higher Q for with reasonable inductance and fr. The bond pad structure using micro-PS can significantly reduce the parasitic bond pad capacitance and increases the crosstalk isolation characteristic. Reducing the parasitic pad capacitance by using micro-PS results in high bond pad resonant frequency of up to 56.2 GHz. The crosstalk between bond pads becomes much smaller than that of conventional p- bulk substrate by using micro-PS. In addition, the use of micro-PS leads to greatly improved transformer performances including higher Q and fr, mutual reactive coupling coefficients with larger useable band-width and maximum available gain by reducing the substrate effect.
Keywords/Search Tags:Substrate, Micro-ps
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