Adaptive-delay sequential circuits

Adaptive Delay Sequential Elements (ADSEs) are a class of sequential elements with electrically tunable timing constraints. ADSEs use PMOS floating-gate Synapse Transistors to tune their internal clock delays.; I develop several ADSEs by augmenting regular flip-flops with an Adaptive Clock Generator (ACC). I develop a simulation model for Synapse Transistors and use it to simulate ADSEs. I also present measured data from prototypes that show ACGs are able to vary their delay over half of the clock period with picosecond accuracy. My experiments show that the ADSE sensitivity to supply voltage and temperature is comparable to non-adaptive flip-flops. I also show that the effects of noise and device mismatch on ADSEs are predictably small. Finally, I present experimental results on retention of programmed delays.; I demonstrate a method for selective tuning of embedded ADSEs using a prototype test chip. I also investigate the area penalty of ADSEs and conclude that the average penalty in block area is about 10%. I discuss the applications of ADSEs in improving fabrication yield and optimizing circuit performance.; ADSEs can minimize clock cycle time by scheduling clock latencies. I review clock scheduling algorithms and show how ADSEs address a common difficulty encountered by all such algorithms. I also use ADSEs to minimize peak power consumption. I formulate a peak-power minimization problem and demonstrate a quadratic programming based solution. I use benchmark circuits to estimate the peak power reduction achievable by my proposed method.; I extend the ADSE concept to build self-tuning circuits. I develop examples of Self-tuning Adaptive-delay Sequential Elements (SASEs) and demonstrate their operation on test chips. I propose a tuning algorithm for SASEs that achieves optimal clock latencies for all flip-flops. I demonstrate the convergence of my tuning algorithm by showing its equivalence to computing a Minimum Mean Cycle (MMC) of a graph. I also discuss Selectable Self-tuning Adaptive-delay Sequential Elements (SSASE) that combine self-tuning capability of SASEs with selective tuning capability of ADSEs.; In future extensions of this work I hope to utilize direct tunneling in more advanced manufacturing technologies to build continuously self-tuning and self-correcting circuits.