| Since the introduction of turbo principle and turbo codes in 1993, a joint equalization and decoding algorithm, turbo equalization, has been proposed to dramatically improve bit error rate (BER) in comparison to conventional (separate) equalization and decoding systems. We first analyze this iterative procedure using linearized BER transfer and extrinsic information transfer (EXIT) charts. The first method is to analytically compute the BER of the soft-input soft-output (SISO) equalizer in two extreme cases (no and perfect a priori information). The second method is to directly evaluate the mutual information at the two end points of an EXIT chart. Then, by modeling BER transfer and EXIT charts as linear, algorithmic behavior of turbo equalization is investigated with reduced complexity in comparison to existing turbo equalization analysis methods.; Iterative equalization and decoding techniques are computationally complex, thereby raising implementation challenges for low-power and high-throughput applications. We present the block-interleaved pipelining (BIP) technique to reduce the critical path delay of a maximum a posteriori probability (MAP) decoder. Such a pipelined MAP decoder is implemented in 1.8-V TSMC 0.18-mum CMOS technology and provides 285 MHz operating speed with 330-mW power consumption. The MAP decoder chip achieves a 1.7x to 2.2x increase in clock frequency with a reduction in logic area over existing 0.18-mum designs. Further, for an example of a turbo decoder, we found that the BIP architecture provided a throughput gain of nearly 200% at a cost of only roughly 60% area overhead and while yielding 20%--40% power savings for a block-interleaving depth of M = 2 along with voltage scaling. For turbo equalizers, the symbol-based BIP architecture enabled a throughput gain of nearly 180% with an area savings of 25%.; Various linear turbo equalizer VLSI architectures are explored. Energy-efficient architectures that eliminate redundant operations and employing early termination achieve power savings up to 60%. To improve the throughput, a concurrent processing VLSI architecture is proposed, where SISO equalizers and decoders are running concurrently, thereby increasing throughput by up to 75%. To improve the BER further, a class of switching linear turbo equalizers is also shown along with several feasible switching schemes. |
