Performance-based dynamic power optimization methodologies for gigabit data links

Aggressive scaling of CMOS technology has enabled exponential on-chip performance improvement and integration density coupled with higher power consumption and design complexity. High-bandwidth and energy-efficient I/O designs are in high demands to further leverage such improvement for system-level performance scaling. This work is to explore a technique to minimize the power consumption of high-speed data links based on link performance.; The proposed power saving methodology uses link bit error rate (BER) as a figure-of-merit to regulate transmit power due to the link performance's dependency on signaling power level. To do so, a negotiation algorithm is developed to track the actual link BER with respect to a target value to fine tune and then minimize transmit driving strength required. This algorithm can be integrated with transceiver design and rerun whenever there is a change to system, enabling the capability of dynamic power optimization for high-speed data links.; Fast and accurate BER measurements are the key part of the performance-based power saving algorithm. Although accelerated bit error rate measurement has been widely adopted to speed up the low BER measurement process that usually take days to weeks using conventional method, it requires specialized lab equipment. To makes "in the field" fast BER testing possible, this work presents an optical transceiver architecture with on-chip accelerated BER measurement mechanics that reduces such low BER testing time to minutes and enhances link built-in self-testability. It uses an integrated interference generator to degrade receiver performance and raise the BER to a range which allows a substantially reduced measurement time. Values of BER vs. the amount of interference are then extrapolated to the point of zero artificial degradation for link actual BER.; Proposed techniques are applied to the design of energy-efficient optical interconnects in very-short-reach applications. Two prototype transceiver chips have been implemented in a 0.5 mum CMOS SOI technology and FPGA-based demonstration systems have been built for testing purpose. At 1.8Gb/s, experiment results show the ability of the algorithm to find the optimum power setting for the link and dynamically relocate the optimum value even after changes made in the system. A close correlation between extrapolated BER value and link actual BER has been observed, which confirms the proper functionality of integrated accelerated BER testing methodology.