Polarization-switching D/A converter

Ferroelectric capacitors have been successfully integrated onto semiconductor IC chips for about one and a half decades, mainly for memory applications. One potential application of integrated ferroelectric circuits is data conversion. In principle, polarization is used as a new medium for data conversion other than the conventional ones (i.e., voltage, current and charge). A ferroelectric material possesses reversible spontaneous polarization and has a large dielectric constant. So a data converter implemented with ferroelectric capacitors has advantages over one with conventional capacitors, resulting from reduced influence of bottom-electrode parasitic capacitance. Furthermore, a data converter based on ferroelectric capacitors has the unique nonvolatile memory function.; This dissertation describes polarization-switching D/A converters (PDACs). Its contents include modeling of ferroelectric capacitors, a proposed PDAC architecture, and the design and experimental results of a prototype device. Fabricated through MOSIS with 1.5 micron CMOS technology, the prototype device contains three 9-bit bipolar PDACs based on linear CMOS capacitors or nonlinear ferroelectric capacitors. While CMOS capacitors are implemented on chip, ferroelectric capacitors are connected off-chip to the prototype device.; Modeling of ferroelectric capacitors is achieved by using exponential decay current to accommodate the remanent spontaneous polarization. The circuit model is comprised of a linear capacitor in parallel with a current source that generates an exponential decay current when polarization reversal takes place. It reflects both the basic capacitive and ferroelectric switching behavior of a ferroelectric capacitor. The model incorporates the capacitance, remanent spontaneous polarization, coercive field, electrode area, and film thickness of a ferroelectric capacitor.; Being a switched-capacitor circuit, the proposed PDAC is implemented with a binary-weighted capacitor array. It converts 1's complement binary codes into a bipolar analog voltage. For a 9-bit bipolar PDAC implemented with on-chip 100 μm × 100 μm linear capacitors, its INL (integral nonlinearity) and DNL (differential nonlinearity) at 10 kHz were 0.26 LSB and 0.23 LSB, respectively. For a 9-bit bipolar PDAC prototyped with off-chip ferroelectric capacitors, its INL and DNL at 20 kHz were −0.85 LSB and 1.05 LSB, respectively. These experimental results show that the proposed PDAC is feasible for both linear and ferroelectric capacitors.