| As semiconductor process nodes continue to shrink, the cost of manufacturing has dramatically risen. Although dependent on many factors, this change can largely be attributed to growth in fabrication and test costs. In fabrication, several challenges emerge: adequate control of process variations becomes more difficult at smaller nodes; higher defect density increases failures from random defects; and, systematic process issues perturb device performances. In testing, increasing levels of device integration now require more expensive automated test equipment (ATE) and more complex tests to achieve adequate test coverage. Together, these challenges negatively affect yield and subsequently raise costs.;The fabrication and test process domains each have a substantive body of existing work and expertise aimed at improving cost efficiency via yield enhancement and test cost reduction, respectively. However, the existing work in these domains is largely ad-hoc. Moreover, there have been no significant studies that examine and leverage data across process and test domains together. Semiconductor manufacturing generates an immense amount of data, from raw silicon to final packaged product and even customer returns. The centralized collection of this data in industry information warehouses presents a promising and heretofore untapped opportunity for this type of integrated analysis.;With a machine learning-based methodology, latent correlations in the joint process-test space could be identified, enabling dramatic cost reductions throughout semiconductor manufacturing. I have focused on three particular problem spaces with my dissertation research: (1) Reduce test cost for analog and RF devices, as testing such circuitry can account for up to 50% of the overall production cost of an IC; (2) develop algorithms for post-production performance calibration, enabling higher yields and optimal power-performance; and (3) develop algorithms for spatial modeling of sparsely sampled wafer test parameters. Moreover, I have addressed all of these problems by introducing a model-view-controller (MVC) architecture, designed to support the application of machine learning methods to problems in semiconductor manufacturing, and to enable research spanning both process and test semiconductor data. |
