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Modeling & development of wirelessly coupled loops for chip-to-antenna communications

Posted on:2014-11-22Degree:M.SType:Thesis
University:Queen's University (Canada)Candidate:Johnstone, Jonathan ClaytonFull Text:PDF
GTID:2458390008950887Subject:Engineering
Abstract/Summary:
This thesis examines the use of two coupled loops as an alternative method of connection for high frequency signals between passive elements on microwave laminates and integrated circuits; replacing traditional interconnect methods such as wire bonds and solder bumps which require costly back end of line processing. The loops harness both electric and magnetic fields in order to create the interconnection, and can be placed around the perimeter of the IC; here they do not interfere with placement of the existing electronics on the chip, or occupy space which may be required for large components such as spiral inductors.;Following model development a prototype system, consisting of a two metallic loops (one located on a low-loss microwave laminate, the other on a 0.13 microm CMOS IC), was fabricated. These loops were then stacked in order to couple the signal from a planar antenna array (printed on the laminate) onto the IC. This antenna-to-chip system was simulated and measured to have center frequencies of 25 GHz and 23 GHz respectively, with a peak gain greater than 5 dBi at the beams broadside (8 dBi in simulation). These results agree quite well, with discrepancies arising primarily from the presence of adhesive between the loops. This adhesive wicked underneath the IC during assembly, which was not accounted for during simulation, but can easily be done so. The radiation pattern from the antenna was measured to have a HPBW of 16 degrees in the elevation plane and 100 degrees in the azimuth plane. These correspond nicely with simulated results and produce a suitable system for automotive radar application; where harsh environments present difficulties to current interconnects such as wire bonds.;A parametric model for these coupled loops was developed in this thesis. This model allows for rapid initial dimension choice when provided a variety of different parameters such as the IC process geometry, and loop stack geometry. Once initial dimensions are obtained from the model, full-wave simulation can be used to finalize the design and examine effects of process design rules such as metal density requirements.
Keywords/Search Tags:Loops, Model
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