| To minimize the power consumption and the area of a dual-antenna MIMO receiver one may naturally conceive the arrangement where a single receive path including radio frequency and baseband sections, is shared between the two antennas, and the switching is performed at a rate of at least the RF channel bandwidth. This dissertation identifies two fundamental issues with this approach. First, the switching rate must accommodate all interferers, since for any switching rate there exists an interferer that corrupts the desired signal. Secondly, channel selection, even for minimum switching rate, will corrupt the receiver output and subsequent switching to recover each antenna signal will not undo this corruption.;A new dual-antenna receiver architecture is introduced that employs quadrature down conversion and complex filtering in a low-IF topology. The principle introduced in this architecture is based on down converting the two antenna signals such that one appears in the positive intermediate frequency range and the other in the negative intermediate frequency range, thus allowing their summation and hence digitization by only one pair of A/D converters. The proposed architecture reduces the number of A/D converters by a factor of two and is versatile enough to be used with antenna diversity, beamforming, as well as MIMO systems. The dual-antenna receiver was implemented for IEEE 802.11a standard with the RF signal at 5.39 GHz. Fabricated in a standard digital 0.18 mum CMOS technology the dual-antenna receiver, whose active area measures 1.9 mm x 1.3 mm, meets the IEEE 802.11a sensitivity requirement for a 64QAM OFDM signal with at least 7 dB of margin. Two synchronized vector signal generators applying a 64QAM OFDM signal to one receiver and a 16QAM OFDM signal to the other receiver with both RF signals at -70 dBm, exhibit -25 dB and -27 dB EVMs for the 64QAM and 16QAM constellations, respectively. The measured voltage gain and noise figure for each receiver are 43 dB and 5.5 dB respectively. The dual-antenna receiver dissipates 30.2 mW, per receiver, from a 1.8-V supply lowest of any prior IEEE 802.11a receiver in 0.18 mum CMOS technology. |
