Switched-active and passive, hybrid filter for resonance-free transient regulation

Passive filters in the form of cascaded stages of filter capacitors along the power supply path have thus far been used to keep the supply voltage at the point-of-load within specification---typically 100-150 mV of allowable droop under step loads of about 100 A at 1-10 A/ns. However, in faster, higher current, lower voltage microprocessors, for example, an all passive solution may not be realizable.; This dissertation describes a switched-active filter used as an auxiliary circuit to a passive filter in order to improve the dynamic load regulation of a power delivery system.; Useful, second-order models are derived for the multistage passive filter about the resonant peaks in impedance. Techniques to design a Switched-Active Filter based on this design-oriented model are described and the SAF is shown to complement the passive filter in order to minimize ringing in the general multistage power delivery system. Specific application of the resulting hybrid filter to a microprocessor power delivery system is described.; The SAF design comprises a switched-capacitor, pre-charged to the right voltage and energy to naturally inject or absorb the current needed to maintain regulation through pre-determined parasitic inductance and resistance. Once the parasitic inductance in the SAF path is determined from layout or loss constraints, analytic design equations yield the other SAF parameters which depend only on the passive filter, the ripple specification and the maximum load current. The design is flexible enough for the additional circuitry to be placed some distance away from the point-of-load and is therefore not constrained in the same way as the passive filter.; The design methodology is tested by means of scaled models of the microprocessor power delivery path. SAF experiments demonstrate a factor of five improvement in load regulation at acceptable losses, 0.1 mu J and 5 mu J with 20 nH and 200 nH DC path inductance respectively, per 1 A step load, even with 20% tolerance on the design parameters. Normalized power loss is about 0.4 W/MHzA. Simulations show feedback control is feasible while revealing some of the issues that need to be considered in practical implementation.