| The speed of the read channel of data storage, such as HDD and DVD, has increased very rapidly in recent days. Accordingly, the speed requirement of ADC has also increased. The high-speed medium-resolution application, full flash architecture has been considered the only possible architecture. However, it is difficult to use conventional full flash architecture for a high-speed 8bit resolution application, since the high input impedance, due to a number of comparators, degrades speed. The input impedance doubles as resolution increases by 1bit. In order to overcome the speed restriction due to the input impedance, a new two-step ADC based on flash architecture with interpolation has been designed. The new architecture, which has multiple THAs and an analog switch matrix, enables us to have an equivalent pipeline operation, thus to obtain digital output at each clock period. Post-layout simulation using 0.18um CMOS technology shows ENOB of 7bit for 87.5MHz at 800MSamples/s. The circuit occupies 0.9mm2 silicon active area utilizing 540mW of power consumption. |
