| Many studies show that bridging defects are major causes of fabrication failures. A bridging fault causes a short circuit between circuit nodes and can be tested by logic testing, which measures the erroneous logic values at the circuit outputs, or by IDDQ testing, which measures the elevated power supply current (called IDDQ). This research spans logic as well as IDDQ testing for bridging faults.;A bridging fault may cause intermediate voltages, i.e., voltages between the logic thresholds (VIH and VIL), at the nodes involved in the bridge. In such cases, the gates in the fanout of the bridging fault site may output the expected or a faulty logic value, but we may not be able to determine which one. Furthermore, different gates in the fanout of the fault of the fault site may interpret the voltage as different logic values. Such bridge fault behavior is sometimes referred to as Byzantine behavior. We developed an accurate resistive bridging fault model to capture the Byzantine behavior. We developed the first fault simulator and ATPG at logic level to generate tests for the resistive Byzantine bridging faults. We demonstrate that the current approaches significantly overestimate coverage and that our methodology can generate additional vectors to achieve high coverage.;IDDQ testing is essential to test quality requirements for today's deep-submicron devices. Studies show many defects in a CMOS device can only be detected via IDDQ testing. One of the key parameters in IDDQ testing is the threshold value of IDDQ. Typically, the value of the IDDQ threshold is determined heuristically.;If the value of IDDQ threshold is set too low, then many devices that have elevated IDDQ but cannot cause logic or timing will be erroneously declared faulty and discarded. Clearly, this causes unnecessary yield-loss. On the other hand, if the value of IDDQ threshold is set too high, devices with defects that cause logic, timing, or some other functional errors can be declared fault free. In such cases, IDDQ testing causes high test-escape. We developed new IDDQ test approaches that minimize test-escape and yield-loss. |
