| Future mobile devices need to support more features than ever before. These devices also need to support emerging communication standards, which have high-throughput requirements for a wide variety of algorithms. To cope with increasing system complexity and shorter design times, there is a shift in the implementation paradigm from hardware platforms that use Digital Signal Processors (DSPs) and custom hardware to fully programmable platforms. Explicitly multithreaded processors provide a platform to exploit the large amounts of thread-level parallelism present in emerging communication applications. Reconfigurable hardware enables devices to adapt to the requirements of new applications. These observations motivate the design of multithreaded DSPs augmented with reconfigurable hardware to meet the high-throughput requirements and to realize the diverse feature sets of emerging communication applications.; This dissertation investigates techniques for adding reconfigurable functional units, called Polymorphic Hardware Accelerators (PHAs), to explicitly multithreaded processors. It proposes architectural support to manage PHAs in a multithreaded, multicore environment. It evaluates throughput improvements due to PHAs for algorithms relevant to the communication domain. This dissertation also presents operations that benefit compute-intensive algorithms in emerging wireless communication systems, and examines their hardware complexity. The proposed technique shows an average speedup of 6.8 on important wireless communication algorithms specified in the Embedded Microprocessor Benchmark Consortium (EEMBC) Telecom Benchmark Suite and Department of Defense's Joint Tactical Radio System Software Communication Architecture (JTRS SCA) Hardware Supplement. It shows an average speedup of 2.6 on compute-intensive, multithreaded algorithms for physical layer processing in the large-scale wireless communication, applications of WiMAX and DVB-T receivers. |
