Energy aware VLSI designs for reconfigurable DSP architectures

Power reduction is one of the most critical issues in reconfigurable designs of mobile systems. With supporting the sufficient flexibility and required throughput, system designers face challenges of minimizing power consumption. This dissertation proposes an energy aware VLSI design for reconfigurable DSP architectures. The design considers the reduction of power consumption in several aspects.; First, we focus on the power reduction of parallel multipliers by coefficient optimization. This technique accurately characterizes and models the actual power consumption of the multipliers. Based on the models, the coefficient optimization finds an optimum set of coefficients patterns to minimize the power consumption of the multiplier.; Two novel designs are presented for power reduction on circuit level. First, we propose a reconfigurable embedded multiplier-and-accumulate (MAC) core for low power DSP system designs. The MAC is reconfigurable with coarse granularity that supports a wide range of digital signal processing applications. The pipeline depth of the MAC is dynamically controlled given the throughput requirement of the application. The depth of pipeline varies at the hardware level that controls the rate of execution to save power consumption. In the following we introduce a supply voltage switching mechanism that eliminates power dissipated by glitches while maintains the speed. The mechanism can be applied to either fully combinational or pipelined array structures such as parallel multipliers and unrolled CORDIC.; Next, we investigate and characterize the array structures for their propagation delay and energy consumption as a function of their physical structures when dual supply voltages are applied. We identify circuits that are highly active in their switches for a specific set of coefficients, which is used in many DSP applications, such as discrete cosine transform (DCT), fast Fourier transform (FFT) and CORDIC. From this characterization, we optimize the energy consumption and performance of arithmetic units to the application-specific input patterns.; Finally, we propose a reconfigurable embedded core architecture targeting on FIR filter, DLMS adaptive FIR filter, (I)FFT and 2D-(I)DCT, which are the most commonly used applications in digital filtering. By greatly reducing the routing resources while maintains the sufficient flexibility for the supported applications, our approach achieves the performance and power efficiency similar to their ASIC equivalents.