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A layered chalcogenide phase change memory device

Posted on:2009-02-19Degree:Ph.DType:Dissertation
University:Stanford UniversityCandidate:Gibby, Aaron MatthewFull Text:PDF
GTID:1448390005455909Subject:Engineering
Abstract/Summary:
Non-volatile memory (NVM) is the fastest growing sector of the semiconductor market. With sales growing from ;As a result, research has accelerated in alternative NVM technologies. Among these, phase-change memory (PCM) shows particular promise given its small cell size, non-destructive read, direct overwrite ability, large sensing margin, and fast speed. Despite these advantages, the requirement for a large (mA-range) programming current remains the major obstacle to mainstream implementation for PCM.;To address this issue, we propose a novel layered structure where the phase-change material (Ge2 Sb2 Te5, or GST) is sandwiched between two other layers (called GST-x layers). With the correct choice of material, the GST-x layers improve the thermal isolation of the GST, while reducing the volume of material programmed. This, in turn, lowers the energy and current required to operate the device.;After a thorough analysis of GST-x candidates using X-ray Diffraction, X-ray Photoemission Spectroscopy, Thermal Reflectance Thermometry, and electrical measurements, GeTe (GT) was chosen to function as the GST-x film. Single layer GST and multi-layer GT/GST/GT devices were then fabricated and compared. Analysis was conducted using a combination of electrical measurements, transmission electron microscopy and scanning Auger spectroscopy.;As a result of this analysis, GT/GST/GT devices showed a modest (24%) reduction in programming current on the first cycle and a significant (99%) reduction on subsequent cycling. Reasons for this and reliability concerns are discussed. Finally, suggestions for further improving the layered structure are presented.
Keywords/Search Tags:Layered, Memory
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