Circuits for secure systems

Secure systems require strong encryption and authentication protocols. Secure systems are used are communications, data storage, identity protection, among others. Two essential components of any secure system are a random number generator and an encryption engine.;The strength of the system is proportional to the entropy of the random numbers used. Pseudo random number generators are the most commonly used for this purpose. True random number generators, which harvest randomness from physical sources, provide an output with high entropy, but they are sensitive to external noise, variations in the environment or malicious tampering.;Encryption algorithms are subject to attacks that strive to disclose the secret keys. The attackers usually rely in the mathematical properties of the algorithm and the side-channel information that is available as the devices are operational, such as current traces, electromagnetic emissions, and I/O signal timing. These attacks are usually timing attacks or power analysis attacks.;This manuscript focuses in the generation of secret keys for encryption and authentication systems using a true random number generator. And the protection of hardware based implementations of encryption systems against power analysis attacks.;We propose a true random number generator with a metastability-based controller that achieves high entropy and passes randomness tests. The generator grades the probability of randomness regardless of the output bit value by measuring the metastable resolution time. Dynamic control enables the system to respond to deterministic noise and a qualifier module grades the individual metastable events to produce a high-entropy random bit-stream. A fully integrated true random number generator was fabricated in a 0.13mum bulk-CMOS technology in 0.145mm2.;Two circuit modules to prevent attackers from disclosing the secret key of AES encryption engines are proposed. An on-chip filter and a current equalizer using switching capacitor modules were demonstrated using an ASIC AES implementation fabricated in 0.13mum CMOS. The on-chip filter has a 5% area overhead and has protected the secret key after 200k encryptions. The current equalizer has 7.2% area, 33% power and 2x performance overheads. The secret key has not been revealed after 2M encryptions.