Energy and Performance Balancing Architecture for Asynchronous Data Processing Platform

The semiconductor industry has been increasingly focused on the energy consumption and heat generation in CMOS-based integrated circuits (ICs) for its dominating impact on the system performance and reliability. Without clock-related timing constraints, asynchronous circuits have demonstrated unique flexibility in performance-energy tradeoffs compared to synchronous designs. This dissertation work presents the architecture capable of balancing energy and performance for asynchronous digital signal processing circuits using the Multi-Threshold NULL Convention Logic (MTNCL). Architecture implementing user-configurable adaptive dynamic voltage scaling (DVS) and data processing core disabling based on the detection and parameterization of system throughput are developed for MTNCL parallel homogeneous and heterogeneous platforms to optimally balance performance and energy efficiency. Simulation results and comparison with previously designed MTNCL homogeneous and heterogeneous platforms implementing only DVS show enhanced coherency between energy consumption and performance, and the improved effectiveness of DVS with core disabling in balancing the energy and performance of both platforms.