Efficient linear CMOS RF power amplification

The advent of high-bandwidth, highly spectral-efficient communication protocols, such as IEEE 802.11g, has imposed tremendous challenges on RF power amplifier design. Since the power amplifier is often the most power-consuming block in a wireless system, its efficiency can have a determining impact on the battery life of the system. However, the high linearity required in many current and emerging wireless systems has typically mandated the use of highly linear traditional class-A designs that have a relatively low efficiency.; This dissertation introduces an approach to CMOS RF power amplifier design that employs a digitally modulated polar architecture to improve the overall power efficiency while providing the linearity required of IEEE 802.11g systems. An implementation of the proposed approach comprises 64 parallel RF amplifiers that are driven by a constant-envelope RF phase-modulated signal. The unit amplifiers are digitally activated by a 6-bit envelope code to construct an RF output with a varying envelope, thus performing a digital-to-RF conversion. It is shown that efficiency of this architecture is proportional to the square root of the output power, in contrast to the linear relationship between efficiency and output power in class-A amplifiers. This results in a factor of 2-3 improvement in average efficiency when amplifying IEEE 802.11g signals. This research also explores the use of oversampling and L-fold linear interpolation to suppress the spectral images that result from the discrete-time to continuous-time conversion of the envelope.; An experimental prototype of the digitally-modulated polar power amplifier has been integrated in a 0.18- m CMOS technology, occupies a total die area of 1.8 mm2, operates at 1.6 GHz and achieves power-added-efficiency (PAE) of 6.7% with a -26.8 dB error-vector-magnitude (EVM) while delivering 13.6 dBm linear OFDM output power. For comparison purposes, the polar amplifier has also been configured as a class-A amplifier by setting all the envelope bits to one and driving the input with a linear OFDM signal. Measurements verify that the efficiency achieved with the polar architecture is more than two times better than the efficiency of conventional class-A design.