| Through-silicon vias (TSVs) provide vertical interconnects for three-dimensional (3D) stacking technology with a potential to significantly reduce the average wire length of block-to-block interconnects. This dissertation discusses the silicon etching techniques involved in making through wafer interconnects using a deep reactive ion etching (DRIE) system. All work was performed at the University of Arkansas High Density Electronics Center (HiDEC). Detailed studies were conducted using the Surface Technology System (STS) DRIE tool to understand the effect of process parameters on via formation in silicon. The process parameters under study include the automatic pressure control (APC) angle, coil power, platen power and gas flow rates for the etch gas (SF6) and passivation gas (C4F8). In addition, the effect of chamber cleaning and conditioning on controlling the via profile was also investigated.;The goal of this program is to develop a three-dimensional packaging technology for High Speed RF Communications. This involves the fabrication of TSVs and the key processes can be divided into the following areas: blind via formation; insulation, barrier, and seed layer deposition; copper (Cu) electroplating; wafer attachment and thinning; and wafer backside processing for contact formation. TSV formation in silicon enables integration of heterogeneous technologies. The main aim of this work is to create blind vias in silicon that can be lined with insulation, barrier, and seed layers followed by metal filling. Other research objectives include modeling of vias using finite element analysis software (ANSYS) and finally work in the area of plasma diagnostics for the DRIE system. |
