Electrical contacts to individual nanostructures and fabrication of nanoscale gaps by feedback controlled electromigration

The transport characteristics of nano---electronic devices are determined not only by the electronic structure of the underlying nanostructure, but also by the detailed properties of the electrode---nanostructure interface and by transport through undesirable parasitic conduction pathways. Because nanoparticle and single molecule devices require the use of nano-scale gaps, they are particularly prone to suffer from parasitic conduction pathways. It has been shown that transport data from both as---fabricated nanogaps and nanogaps combined with nanostructures can exhibit signatures of quantum transport such as Coulomb blockade and the Kondo effect.;We investigate electronic devices that require nanogaps smaller than the resolution of electron beam lithography (<25 nm) and develop a technique of feedback controlled electromigration (FCE) to make nanometer---spaced electrodes in ambient lab conditions. Nanogap formation occurs through three regimes: a bulk---behavior regime where electromigration is triggered at constant temperature, a few-atom regime with conductance characterized by conductance quantum plateaus and jumps, and a tunneling regime across the nanogap once the conductance falls below the conductance quantum G0 = 2e2/h. To permit the use of transmission electron microscopy (TEM) to image the gaps, we fabricated nanogaps on free-standing transparent SiNx membranes. The electrodes are found to be clear of any apparent debris and are stable on the order of hours. Real-time transmission electron microscopy of nanogap formation by FCE reveals a remarkable degree of crystalline order. Crystal facets appear during FCE indicating a layer-by-layer, highly reproducible electromigration process that avoids thermal runaway and melting. Additionally, we describe investigations of dielectrophoretic (DEP) assembly of nanogap electronic devices based on single Au nanoparticles (AuNPs). A symmetric electrical circuit design suitable for DEP on oxidized Si and SiNx substrates is developed. A 3 V threshold for AuNP assembly and melting of AuNPs with diameter <10 nm are consistently observed. Finally, we have developed a technique for simultaneously fabricating large numbers of nanogaps in a single processing step using FCE in a balanced simultaneous process that uses a novel arrangement of nanoscale shorts with resistances <4 O between junctions. Parallel processing opens a new route towards the manufacture of complex circuits.