Test pattern generation techniques that target low test application time

The dissertation investigates and proposes techniques to reduce test application time and time to market test requirements. Test generation techniques for logic and delay faults in digital circuits are presented.;For logic defects, concurrent test generation in multi-core System on Chip to reduce test application time is proposed. The Single Stuck-at Fault model is considered.;For timing defects, a compaction technique based on implicit path removal is proposed. The Path Delay Fault model is considered. Also, a test generation technique for sequential (non-scan) circuits proposed.