Indium gallium arsenide MOSFETs with 5 nm channel and self-aligned source/drain by MBE regrowth

InGaAs has been extensively studied as a potential channel material for sub-22nm gate length VLSI MOSFETs because of its low electron effective mass (m*) hence high electron velocity (v). At 22 nm gate lengths, a maximum 1 nm EOT dielectric and 5 nm thick channel with strong vertical confinement are required for low subthreshold swing and low drain induced barrier lowering (DIBL). Most reported InGaAs MOSFETs and HEMTs have typically ≥ 10 nm channel thickness. The source/drain (S/D) junctions must be very shallow (∼ 5 nm) with abrupt vertical and lateral profiles, yet extremely low (∼ 50 O -- mum) source access resistance and consequently very low (∼ 1 O mu m2) contact and (∼ 400 O/□) sheet resistivities are required to minimize degradation of the drive current ( Id) and transconductance (gm). Such parameters are difficult to achieve in InGaAs by ion implantation of the n+ source/drain, particularly if an InAlAs bottom confinement layer is used. Source/drain contacts must also be self-aligned to the gate, yet there is no known equivalent of self-aligned silicides in III-V materials. This dissertation addresses these requirements and shows InGaAs MOSFETs with self-aligned S/D access regions and self-aligned metal contacts formed by MBE regrowth and in-situ metal deposition.;A scalable all dry etch gate process with minimal damage to thin channel layers was developed. A ex-situ and in-situ clean of the wafer leaves a contamination free channel surface suitable for epitaxial regrowth. Self-aligned source/drain regions were defined by MBE regrowth. Self-aligned in-situ Mo contacts were defined by 25 nm SiNx sidewalls and a height selective etch. MOSFETs were demonstrated with this process with ∼ 5 nm channel. The source/drain regrowth process is optimized and an InAs source/drain regrowth process was developed. The 200 nm Lg device showed 0.7 mA/mu m peak drive current at Vgs = 4.0 V and Vds = 1.0 V with 2.5 nm EOT and has an on resistance of 600 O -- mum. The technology shows the potential to scale to sub-22nm gate lengths.