Scalable test generation for path delay faults

Modern day IC design has drawn a lot of attention towards the path delay fault model (PDF) [1], which targets delay defects that affect the timing characteristics of a circuit. Due to the exponential number of paths in modern circuits a subset of critical paths are chosen for testing purposes [2]. Path intensive circuits contain a large number of critical paths whose delays affect the performance of the circuit. This dissertation presents three techniques to improve test generation for path delay faults. The first technique presented in this dissertation avoids testing unnecessary paths by using arithmetic operations. The second technique shows how to compact many faults into a single test application, thus saving valuable test application time. The third technique demonstrates how to generate tests under modern day scan architectures. Experimental results demonstrate the effectiveness of the proposed techniques.