VLSI architectures for MIMO detection

Multiple-Input Multiple-Output (MIMO) communication is a rapidly developing wireless technology that promises wireless access with unprecedented data rates to multiple users at high quality of service (QoS). These benefits stems from employing multiple antennas on both sides of the wireless channel and transmitting multiple data streams concurrently and in the same frequency bands, implying higher channel capacity and link reliability. One of the main challenges in practical realization of MIMO wireless systems lies in the efficient implementation of the MIMO detectors.;Depth-first-K-Best (DFKB) sphere detection algorithm is proposed to overcome major short comings of the classical depth-first sphere decoding algorithm in throughput performance and memory space requirements. A folded architecture implementation of this algorithm based on MECU processing element achieves a maximum throughput of 672 Mbps and supports combinations of antenna configurations (4x4, 3x3, 2x2) over a configurable range of modulation modes (BPSK, QPSK, 16-QAM and 64-QAM). Fixed sphere decoding algorithm is a sub-optimal fixed throughput detection algorithm that can be implemented in hardware using an array of MECU processing elements. An array processor for a 4x4 (8-1-1-1) decoder based on MECU is able to achieve a maximum throughput of 3600 Mbps.;In case of breadth-first detectors, it is shown that by applying 2-stage node elimination algorithm instead of the strict K best search, the overall algorithmic and architectural complexity of the complex-valued K-best detector can be reduced significantly. A complex-valued pipelined VLSI architecture for K-best algorithm using MECU processing elements is designed and implemented. The implementation results for a 4x4 (QPSK, 16-QAM and 64-QAM) detector compared to real-valued reference detector shows 53% decrease in silicon complexity and 75% increase in maximum clock frequency. Implementation of the proposed complex-valued K-best detector in CMOS 0.13 mum technology achieves up to 1680 Mbps throughput at 107K gates.;In order to demonstrate and evaluate performance of DFKB-MECU architecture, a configurable 4x4/3x3/2x2 64-QAM/16-QAM/QPSK/BPSK ASIC detector has been designed and routed in CMOS 0.18 mum technology. The core area of the detector is 0.87mm2 and it can achieve a throughput of 288 Mbps.;This dissertation covers design and implementation of high performance MIMO detectors. In particular tree search based detection algorithms are studied as the basis for developing new detection algorithms and architectures. A new approach has been proposed for design of MIMO detectors based on a configurable processing element that can be utilized in different configurations for implementation of tree search based detection algorithms. Based on a novel enumeration algorithm for M-QAM constellation space, a low complexity dynamically configurable processing element (MECU) that can be used as the main processing element for implementation of various MIMO detectors has been designed. The MECU processing element can be dynamically configured to support BPSK, QPSK, 16-QAM and 64-QAM modulation and is characterized by a low silicon complexity equivalent to 18K gates.