| Discrete Fourier Transform (DFT) is the most important operation in digital signal processing (DSP). It is widely used in many applications, such as Orthogonal Frequency Division Multiplexing (OFDM), spectrum analysis, and radar image processing. Furthermore, many digital signal processing algorithms can be realized by DFT, such as convolution, spectrum estimation, and correlation. But in practice, DFT is difficult to be fulfilled directly since the amount of calculation of DFT is complex. To reduce the amount of calculation, Cooley and Tukey proposed the well-know Fast Fourier Transform (FFT) algorithm, which reduces the amount of calculation of N-point DFT from O( N2) to O( N2 log2N). Based on Cooley and Tukey's algorithm, many other FFT algorithms have been developed for different applications.;In practice, as VLSI technology evolves, hardware realization of FFT processors are more widely used to achieve real-time FFT processing. In VLSI realization of an FFT processor, speed, area and power consumption are three design metrics to evaluate the performance of an FFT processor. Therefore, in this study, we propose novel implementation techniques and architectures to improve the performance of the FFT processors; mainly focusing on radix-2 and radix-4 FFT algorithms First, we propose a new memory addressing scheme for faster radix-2 FFT engines. This design consumes less power and hardware resources than the existing algorithms. Another proposed method enhances this FFT engine, by reducing the power consumption even more by limiting the memory access frequency with a careful arrangement of memory banks. We also propose a new design for higher radix FFT, which increases the processing speed than the existing algorithms. At last, a new CORDIC-based FFT design is presented to realize less area and low power FFT processors. |
