On the power management of multi-core processors with network on chip

In this work, we introduce one of the early power management policies that considers both the processing elements as well as the Network on Chip (NoC) under a multi-core processor while optimizing power consumption at runtime. We emphasize the importance of considering the NoC in addition to the processing elements by comparing the power savings achieved by our policy to existing works that only consider the processing elements. We utilize dynamic optimization mechanisms that involve prediction while introducing minimal performance overhead. Our policy is also reliability aware as it limits the magnitude of the thermal cycling experienced at different cores within the multi-core processor.;We also ported our power management policy to a 3D multi-core platform by augmenting it with the capability to address the challenges that might not be present under 2D multi-core processors. Here a thermal management policy that considers the different cooling requirements as well as the different thermal correlations between cores at different layers is introduced. In addition, our 3D multi-core platform incorporated a temperature aware routing algorithm that considers the temperature of the cores before routing any messages.;We demonstrate the effectiveness of our techniques by conducting numerous experiments using a full system simulator which integrated a memory model, NoC model, NoC power model, processor power model, as well as a thermal model. In addition, our simulation platform executed the latest multi-threaded benchmarks [38] from Princeton. The results of our numerous experiments demonstrated a clear superiority of our policies in optimizing the power/performance/tradeoff under both 2D as well as 3D multi-core processors.