Design of scaled electronic devices based on III-V materials

One of the challenges faced by the continuous scaling of MOSFETs, is to reconcile the demands for both high speed performance and low power dissipation. The device design space to meet these two criteria using conventional embodiment of the Si bulk MOSFET structure is gradually shrinking, and thus the conventional embodiment may not be able to support the scaling towards the end of the SIA roadmap. In this dissertation, a viable solution from device design perspective to extend the semiconductor device scaling is envisioned, by exploiting the superior material properties and material versatility of the III-V semiconductor family. On a short term basis, by replacing the Si material by high mobility III-V material (such as InGaAs) may help address the demand for high speed performance. The device involved here continues the theme of planar structure with fully depleted thin body. Various design issues are addressed in the dissertation associated the introduction of the new materials. On the intrinsic device side, much attention has been given to the reduced density of states (DOS) associated with these low effective mass materials. Analysis and discussions are presented here that illustrate device design strategies to circumvent the drawbacks resulting from the small DOS. On the extrinsic side, the incorporation of high-k dielectric has led to non-ideal characteristics at the semiconductor/dielectric interface, which is analyzed in the dissertation to assist in pinpointing the associated technical problem. For further scaling, more attention must be directed to the control of short channel effects (SCEs). Therefore, the natural next step from a planar III-V MOSFET may be a nanowire III-V MOSFET that takes advantage of gate-all-around configuration. However, due to the one dimensional nature of the nanowire, the device performance must be reevaluated with 1-D transport physics. To further proceed, especially to curb the power consumption, it is necessary to scale down the supply voltage, which however undermines performance traditionally. To reconcile these requirements, a tunneling FET based on III-V staggered heterojunctions is introduced. Simulation study has shown that significant current (∼0.4mA/mum) may be achieved over a supply voltage of 0.3V with 104 on-off ratio. In summary, in this dissertation, a variety of feasible solutions towards the end of roadmap from device design perspective are presented.