| In order to reduce the pin count of chips and the complexity of the routing on printed-circuit boards and backplanes, it is desirable to replace a large number of parallel channels with a few serial links. Such a transformation can also potentially save significant power because it maintains the I/O voltage swings and termination impedances relatively constant. It is therefore plausible that data rates approaching 20 Gb/s will become common in the near future. At these speeds, the loss of FR4 boards poses a great challenge, requiring heavy equalization. From circuit design point of view, it is simpler to employ linear equalization (in the transmitter and the receiver), but from system design point of view, two serious issues make this approach unattractive: the amplification of crosstalk and the lack of ability to equalize for impedance discontinuities (sharp notches in the channel frequency response). In an optimum, yet practical system, one would place 4 to 5 dB of linear equalization in the transmitter and a similar amount in the receiver, and perform the remaining equalization by means of a decision-feedback equalizer (DFE), thus alleviating both issues. This work presents a 20-Gb/s serial link equalizer capable of compensating 24 dB of channel loss at 10 GHz. It consists of a linear equalizer with 9 dB of boost and a 1-tap speculative half-rate DFE. It generates an output with a BER less than 10-12 and an eye opening of 0.32 UI. It draws 40 mW from a 1-V supply at 20 Gb/s. |
