| With the introduction of multi-core processors, a balance between access contention of the cache and availability of cached data for multiple cores has to be addressed. Processor manufacturers are finding this compromise through a combination of private and shared cache structures, where the last level cache (LLC) may not be shared across all processing cores. The hardware enhancement presents a NUCA-like (non uniform cache access) environment, with hierarchical memory access time between the cores and the caches. This poses an interesting optimization opportunity for the operating system in ensuring minimum access time to the memory for optimal performance.;This dissertation proposes a solution by augmenting an existing scheduling domain hierarchy to be aware of the relationship between the processing cores and their respective LLCs in order to achieve improved performance. The enhancement targets the abstraction of the LLC, which is a highly contended resource. With the enhanced processor abstraction by the operation system, the scheduler is able to recognize the core-cache topology precisely, thus making better scheduling and load balancing decisions. The implementation of the scheduling domain hierarchy on a full system stack is described and its effectiveness is evaluated. |
