| As the technology scaling approaches to the nanometer scale, high performance micro-processors evolution are hindered by many challenges. Among them, the large leakage power and high run-time temperature are major issues for designers to deal with. Large power density increases the temperature dramatically, and high temperature will increase the leakage power in exponential rate in return. Without efficiently control the temperature, the processor will soon be shut down to avoid permanent physical damage. Further more, the process variation due to the inability to control the fabrication process has put an extra burden for designer to correctly estimate their optimization.; This dissertation proposes to provide a power/thermal evaluation platform for modern microprocessors at the micro-architecture level. And it also proposes to provide two low power, low temperature and high reliability solutions for SRAM structures. As these function units are found to be power hungry and thermal dangerous in the chip.; In particular, this dissertation presents the following studies and designs. On a real Pentium 4 processor, a set of methodology is presented to evaluate the run-time power consumption and temperature distribution of the CPU. By using this method, we presents extensive thermal profiles on 22 SPEC2K benchmarks. Our observations uncover some interesting new thermal features that were difficult to obtain before. Based on our observations, we proposes two dynamic management techniques to improve the power/thermal problems of two SRAM structures, one is the integer register file, and the other is level one cache. The low power register file design we proposed can reduce the leakage current on the read bitline without sacrificing the CPU performance. For the cache, we propose a dynamic subarray permutation scheme to swap the workload on a hot subarray to a cold subarray, such that the peak temperature can be reduced, and cache reliability increased as well. |
